1. Field of the Invention
The present invention relates to a silicon-on-insulator semiconductor device and, more particularly, to an silicon-on-insulator metal-oxide-semiconductor field effect transistor (MOSFET) and also to a method of fabricating the device.
2. Discussion of the Related Art
The term silicon-on-insulator collectively refers to device isolation technologies through which a device fabricated on a silicon substrate is electrically isolated from other devices on the substrate by means of an insulating region bordering the device. Although the origin of silicon-on-insulator technologies may be traced back to a 1934 German patent issued to Oscar Heil, silicon-on-insulator substrates escaped categorization as exotic materials only in the 1980's and were introduced into high-volume production for a limited range of applications only in the early 1990's. Of the many processes that were proposed during the 1980's for fabricating thin-film silicon-on-insulator structures, only SIMOX (Separation by IMplanted OXygen) processes appears to have survived scale-up to high-volume production.
SIMOX processes, in which a buried layer of SiO.sub.2, is created within a silicon substrate by implanting oxygen into the substrate and then annealing the substrate, require implantation of a dose of oxygen ions (typically b 1-2.times.10.sup.18 cm.sub.-2) high enough to ensure that a continuous layer (i.e., a layer without holes which is sufficiently thick and of sufficiently high quality to electrically isolate the device which it borders) of stoichiometric SiO.sub.2 is formed by chemical reaction of implanted oxygyen with bulk silicon during the annealing process. (A lower dose of nitrogen ions may alternatively be implanted in lieu of oxygen ions in order to form a continuous layer of stoichiometric Si.sub.3 N.sub.4.) The energy of the implant must also be sufficiently high (typically 150-200 keV) to ensure that the peak of the implant is sufficiently deep (typically 0.3-0.5 .mu.m) within the substrate to enable device fabrication on the silicon layer that lies above the buried oxide layer.
A post-implant anneal is performed in an inert ambient for a time interval long enough (typically 3-6 hours) and at a temperature high enough (typically 1200-1400.degree. C.) to form the continuous buried layer of stoichiometric SiO.sub.2. In addition to driving the chemical reaction of silicon and oxygen, the anneal facilitates diffusion of unreacted oxygen out of the substrate, thereby increasing the dielectric breakdown strength of the buried oxide layer, and also repair of the region of the crystalline substrate through which the oxygen beam has passed.
After the anneal, the crystalline silicon layer above the buried oxide layer is typically only 100-300 nm thick. Growth of an additional layer of epitaxial silicon would thus be necessary for structures that require thicker single-crystal device regions. Thin-film MOS devices fabricated on a silicon-on-insulator substrate do, however. have several important advantages over devices fabricated on a thicker layer of single-crystal silicon. Long-channel behavior can be preserved for gate lengths well below half a micron because the source/drain depletion regions can obviously extend into the thin film only until they reach the buried oxide layer. Few hot-carriers (i.e., carriers whose energy distribution is shifted to a much higher mean energy than that of carriers which are in thermal equilibrium with the lattice) are generated in such fully-depleted silicon-on-insulator MOSFETs on account of the significantly reduced lateral electric field near the drain edge of the channel.
The performance of thin-film MOSFETs suffer, however, from parasitic effects, notably high sheet resistance of and high contact resistance to the thin film source/drain regions. In addition, MOSFET structures fabricated on silicon-on-insulator substrates are subject to floating-body effects, which occur because the body of the active (device) region of the silicon-on-insulator substrate (ie., the region of the substrate above the buried oxide layer) is not easily held at a constant potential, in contrast to the body of a bulk single-crystal silicon substrate (i.e., a substrate without a buried oxide layer), the back surface of which can easily be grounded. For example, channel electrons in an n-channel MOSFET operating in the saturation region of the I.sub.DS -V.sub.DS characteristics generate electron-hole pairs by impact ionization near the drain region. Absent a grounded body contact, the holes thereby generated would flow towards the source region and increase the substrate potential, which increase would be reflected in an abrupt rise in the I.sub.DS -V.sub.DS characteristics.
An interesting approach to ameliorating floating body effects in a MOSFET fabricated on a silicon-on-insulator substrate was disclosed by K. Hieda, et al. in Floating-Body Effect Free COncave Silicon-on-insulator-MOSFETs (COSMOs), which appeared at pp. 667-670 of the Technical Digest of the IEEE International Electron Devices Meeting held Dec. 8-11, 1991 in Washington, D.C. As shown in the idealized cross-sectional view of FIG. 1, the silicon-on-insulator MOSFET of Hieda, et al. includes:
a lightly-doped, p-type silicon substrate 10 having a trench 13; PA1 a first trench isolation structure 19a within the substrate to a first side of the trench 13; PA1 second trench isolation structures 19b within the substrate to either side of the trench 13, a second trench isolation structure between the trench 13 and the first trench isolation structure 19a; PA1 a conformal gate insulator 16 which lines the trench and thus defines a lined trench; PA1 a gate electrode 17 on the gate insulator 16. which gate electrode fills the lined trench; PA1 lightly-doped, n-type source/drain regions 18a within the substrate to either side of the trench 13, each lightly-doped source/drain region 18a between the trench 13 and a second trench isolation structure 19b; PA1 heavily-doped, n-type source/drain regions 18b within the substrate to either side of the trench 13, each heavily-doped source/drain region 18b above a lightly-doped source/drain region 18a; PA1 a heavily-doped, p-type body-contact region 18c within the substrate between the first trench isolation structure 19a and the second trench isolation structure 19b to the first side of the trench 13; and PA1 a continuous, substantially planar buried silicon dioxide layer 11 within the substrate, which buried layer separates an upper region 10b of the substrate from a lowser region 10a of the substrate and which also bounds from below the first trench isolation structure 19a, the second trench isolation structures 19b, and the trench 13.
The trench 13 is said to be bounded from below by the buried layer 11, since the upper boundary of the buried layer under any given point on the surface of the substrate lies below the lower boundary of the trench under that given point.
The heavily-doped, p-type region 18c of Hieda, et al. is referred to as the body-contact region of the silicon-on-insulator MOSFET, since it provides a low-resistance, electrically conductive path between ground and the upper substrate 10b. Since, as mentioned briefly above, the electrostatic potential of the body would float were it not for an electrically conductive path, the body contact region 18c reduces floating-body effects. The MOSFET structure of Hieda, et al. also provides thick-film source/drain regions 18a and 18b, which facilitate formation of low-resistance electrical contacts to the source/drain regions, and a thin-film channel (i.e., the region of the upper substrate 10b between the bottom of the trench 13 and the buried oxide layer 11), which forestalls the onset of short-channel effects and suppresses the generation of hot electrons.
Notwithstanding the several advantages of the silicon-on-insulator MOSFET structure of Hieda, et al. seen in simulation, such advantages would not easily be realized in practice, since the structure would be very difficult to fabricate. More specifically, the structure of Hieda, et al. provides no etch stop indicator which could be employed during the course of etching the trench 13, the single most important feature of the structure.